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SPDS106A SP
Voice Engine
SEP. 05, 2001 Version 1.0
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPDS106A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 4. APPLICATION FIELDS ............................................................................................................................................................................... 3 5. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 6. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 6.1. DATA RAM MAPPING.............................................................................................................................................................................. 5 6.2. PWM .................................................................................................................................................................................................... 5 6.3. SPC MAPPING ...................................................................................................................................................................................... 5 6.4. RTC (REAL TIME CLOCK)....................................................................................................................................................................... 5 7. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 6 7.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 6 7.2. DC CHARACTERISTICS (VDD = 4.5V, TA = 25).................................................................................................................................... 6 7.3. THE RELATIONSHIP BETWEEN THE ROSC AND THE SYSTEM CLOCK (FOSC) ................................................................................................. 7 7.4. IOA, IOB, IOC, IOD I/O DRIVING CHARACTERISTIC ............................................................................................................................... 7 8. APPLICATION CIRCUITS........................................................................................................................................................................... 8 8.1. APPLICATION CIRCUIT - (1)..................................................................................................................................................................... 8 8.2. APPLICATION CIRCUIT - (2)..................................................................................................................................................................... 9 8.3. APPLICATION CIRCUIT - (3)................................................................................................................................................................... 10 9. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 11 9.1. PAD ASSIGNMENT ................................................................................................................................................................................11 9.2. ORDERING INFORMATION ......................................................................................................................................................................11 9.3. PAD LOCATIONS.................................................................................................................................................................................. 12 10. DISCLAIMER............................................................................................................................................................................................. 13 11. REVISION HISTORY ................................................................................................................................................................................. 14
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
2
SEP. 05, 2001 Version: 1.0
SPDS106A
VOICE ENGINE
1. GENERAL DESCRIPTION
SPDS106A, a single chip contains an 8-bit RISC microprocessor (CPU) and a 16-bit digital signal processor (DSP), is applied for constituting long duration audio applications. memory-mapped (parallel interface). general I/Os to access external devices. audio data. The CPU transmits commands and data to DSP by the means of The CPU employs 23 The 256K x 8 ROM
RTC (Real Time Clock)
3. BLOCK DIAGRAM
The integration method of CPU and DSP is using a shared memory block in between two processors and each register or I/O in CPU will correspond to specified register in DSP. DSP. The following diagram simply describes the access between CPU and
hold the system control program, audio processing program and The DSP receives the commands and data from Both CPU CPU and finally runs the decompressing algorithm. and DSP share a PWM output for audio.
CPU
DSP CPU View DSP View
2. FEATURES
! 8-bit RISC microprocessor (CPU) with 256K bytes ROM for program and audio data. ! CPU with 128 working RAM ! 23 general I/Os ! 7 interrupt sources ! Key change wake up ! 2Hz, 1sec, 2sec, 10sec, 30sec, 1min, 2min or 4min programmable RTC wake up and interrupt. ! Shared D/A converter supports three PWM modes: 10-bit Push-Pull mode 10-bit Single-pin double-ended mode 9-bit single-pin single-ended mode ! Single clock: Crystal OSC or ROSC 20MHz to DSP and 20MHz divided by N to CPU, where N = 2, 4, 6, 8, 10, 12, 14 ! Volume control function ! Serial interface I/O ! CPU with two 12-bit timers/counters ! Low voltage reset ! Sleep mode for power saving ! Multi-phase for remote control application ! Max. CPU clock: 5.0MHz @ 2.4V - 5.5V ! SACM_S480, SACM_S720, SACM_S240, SACM_A2400/A3200 and FM synthesizer
Data Bus Address
(mapping) I/O Registers I/O Registers
Address
Data Bus
4. APPLICATION FIELDS
! Long Duration Audio System ! Intelligent Talking Toys ! Talking Instructions ! Kid-Story Books ! And relevant applications
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3
SEP. 05, 2001 Version: 1.0
SPDS106A
5. SIGNAL DESCRIPTIONS
Mnemonic VDD VSS XI/R XO AUDP AUDN TEST1 TEST2 PIN No. 8, 16 7, 23 21 22 2 4 24 19 Type I I I O O O I I Description Power for chip except shared PWM (Two VDD pins) Ground for chip except shared PWM (Two VSS pins) X'TAL OSC input or ROSC X'TAL OSC output Push-Pull and single pin PWM output (shared) Push-Pull PWM output (shared) Test input, internal pull low, NC Test input, internal pull low, NC
RESET IOA3 - 0 IOB3 - 0 IOC6 - 0 IOD7 - 0 VDD1 VSS1 TEST3 X32I X32O
20 37 - 40 33 - 36 9 - 15 25 - 32 1, 5 3 6 18 17
I I/O I/O I/O I/O I I O I O
Reset input (Active low), internal pull high Programmable I/O pin Programmable I/O pin Programmable I/O pin Programmable I/O pin Power for AUDP and AUDN (Two VDD1 pins) Ground for AUDP and AUDN TEST pin, NC 32768Hz X'TAL input (for RTC function) 32768Hz X'TAL output (for RTC function)
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4
SEP. 05, 2001 Version: 1.0
SPDS106A
6. FUNCTIONAL DESCRIPTIONS
6.1. Data RAM Mapping 6.1.1. DSP
*I/O PORT: *MEMORY MAP (From ROM view) $0002 $0003 $0004 $0005 $00100 UNUSED $00200 *NMI SOURCE: INTA (from TIMER A) $00600 USER'S PROGRAM & DATA AREA ROM BANK #0 $08000 ROM BANK #1 $10000 ROM BANK #2 $18000 ROM BANK #3 $1FFFF $20000 ROM BANK #4 SUNPLUS TEST PROGRAM $00080 USER RAM and STACK $00000 HW register, I/ Os
6.3. SPC Mapping
$0000 Internal Working RAM $07FF $0800
PORT IOA IOB IOC IOD
I/O CONFIG $0000 $0001
Exteranl data RAM shared with CPU
*INT SOURCE: INTA (from TIMER A) INTB (from TIMER B)
$EEEF $FF00 See Below $FF07 $FF08 Memory Mapped I/O $FFFF
FF00: PWM_WR FF01: PWM_SET FF02: TM1_WR & TM1_RD FF03: TM2_WR & TM2_RD
Note: Sunplus products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of the President of Sunplus.
RTC CPU CLK / 1024 CPU CLK / 8192 CPU CLK / 65536 EXT INT
$38000 ROM BANK #7 $3FFFF
6.4. RTC (Real Time Clock)
Some applications require a real time clock for time tracking. SPDS106A provides a RTC based on 2Hz, 1sec, 2sec, 10sec, 30sec, 1min, 2min or 4min programmable frequency. SPDS106A 2-second, provides 10-second, programmable 30-second, 1/2-second, 1-minute, 2-minute The and 1-second,
6.2. PWM
SPDS106A offers one set of PWM output for CPU and DSP. Three PWM modes include Push-Pull, Single-pin Double-ended and Single-pin Single-ended.
4-minute wake-up sources, the system wakes up every specified wake-up source and users can use it as the time tracking resource. In addition, SPDS106A supports 32768 OSC strong mode and auto mode. With strong mode, 32768 OSC always runs in the With auto mode, the first 2-second is strong highest power.
mode and then switch to weak mode to save power.
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
5
SEP. 05, 2001 Version: 1.0
SPDS106A
7. ELECTRICAL SPECIFICATIONS
7.1. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply Voltage Input voltage Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
VDD VIN TA TSTG
+0.0 -0.3 0 -55
to to to to
<7.0 VDD +0.3 55 125
V V

For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
7.2. DC Characteristics (VDD = 4.5V, TA = 25)
Characteristics Symbol Limit Min. Typ. Max. Unit Test condition
Operating Voltage Operating Current Standby Current Oscillation Resistor System Clock CPU Clock Input High Voltage Input Low Voltage Output High Current (IOA - IOD) Output Low Current (IOA - IOD) Input Pull High Resistor (IOA) Input Pull Low Resistor (IOD)
VDD IOP ISTB ROSC FSYS FCPU VIH VIL IOH IOL RINH RINL
2.4 1.4 0.7*VDD VSS -
17 36.5 20 -3.0 7.5 64 24
5.5 2.0 5.0 VDD 0.2*VDD -
V mA
A
FOSC = 20MHz @ 4.5V, no load VDD = 4.5V VDD = 4.5V, FSYS = 20MHz
K MHz MHz V V mA mA K K
VDD = 4.5V VOH = 4.0V VDD = 4.5V VOH = 0.6V VDD = 4.5V VIN = 0.7*VDD = 3.15V VDD = 4.5V VIN = 0.2*VDD = 0.9V
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SEP. 05, 2001 Version: 1.0
SPDS106A
7.3. The Relationship between the ROSC and the System Clock (FOSC)
Fosc vs. VDD
21.0
7.4. IOA, IOB, IOC, IOD I/O Driving Characteristic
IOH vs. VOH 1 Output Current (IOH) 0 -4 -8 -12 -16 Output Voltage (VOH) 1.5 2 2.5 3 3.5 4 4.5
Fosc (MHz)
20.5 20.0 19.5 19.0 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 5.8
VDD (V)
Fosc vs. Rosc (@VDD=4.5V)
30
Fosc (MHz)
25 20
IOL vs. VOL Output Current (IOL) 20 16 12 8 4 0 0 0.5 1 1.5 2 2.5 Output Voltage (VOL)
15 10
28 30 32 34 36 38 40 42 44
Rosc (K)
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SEP. 05, 2001 Version: 1.0
SPDS106A
X'TAL/CERAMIC OSC VDD R1
C3 20p 20p
C4
20p*
Resistor
XI/R IOA3-0 IOA (I/O) X32I 20p IOC (I/O) X32O 20p IOC6-0
XO
IOA3-0 IOC6-0
XI/R IOA (I/O) IOC (I/O)
XO
X32I
20p
X32O
SPDS106A
TEST1 TEST2 IOB3-0 IOB(I/O) IOD7-0 IOD (I/O) VDD(16) VDD(8) 0.1 VSS(7) VSS(23) R1 VDD AUDN RESET AUDP (1)VDD1 (5)VDD1
SPDS106A
TEST1 TEST2 IOB3-0 IOB(I/O) Speaker ~16 IOD7-0 IOD (I/O)
20p
AUDP
(1)VDD1
(5)VDD1 0.1 (3)VSS1 0.1 VSS(7) VSS(23) R1 VDD VDD(16) VDD(8)
Speaker ~16
0.1
(3)VSS1
RESET
8. APPLICATION CIRCUITS
50K
50K C5 RESET 0.1 C5 VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground 0.1
SPDS106A Application circuit (PWM Push-Pull Output)
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
RESET
VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground
Note: Capacitor may be increased if necessary. (Cmax = 120p)
AUDN
8.1. Application Circuit - (1)
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SEP. 05, 2001 Version: 1.0
SEP. 05, 2001
VDD C4 20p 20p* R1 Resistor X32I 20p X32O 20p VDD Battery VDD IOA3-0 IOC6-0 IOC (I/O) TEST1 XI/R IOA (I/O) XO TEST2 1K 1K 1K 1K 47 0.1 0.1 470 8050 10K 47 IOB3-0 IOB(I/O) IOD7-0 IOD (I/O) VDD(16) VDD(8) 0.1
SPDS106A
X'TAL/CERAMIC OSC
C3 20p
IOA3-0 IOA (I/O) IOC6-0 IOC (I/O) TEST1 TEST2 IOB3-0 IOB(I/O) IOD7-0 AUDP AUDN IOD (I/O) VDD(16) VDD(8) 0.1 VSS(7) VSS(23) R1 VDD 50K C5 (3)VSS1 RESET (1)VDD1 (5)VDD1
XI/R
XO
X32I
20p
X32O
VDD
Battery VDD
20p
SPDS106A
SPDS106A
(5)VDD1
(1)VDD1
1K
10K
AUDP
1K
47
AUDN
1K
1K
47
8050
0.1 VSS(7) VSS(23) R1 VDD 50K C5 RESET VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground
0.1
470
(3)VSS1 RESET
8.2. Application Circuit - (2)
RESET 0.1 0.1
(c) Sunplus Technology Co., Ltd.
SPDS106A single-pin double-ended mode application circuit
Proprietary & Confidential
VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground
Note: *Capacitor may be increased if necessary. (Cmax = 120p)
9
Version: 1.0
SEP. 05, 2001
VDD C4 20p R1 20p* Resistor X32I 20p VDD 20p Battery VDD IOA3-0 IOC6-0 IOC (I/O) TEST1 XI/R IOA (I/O) XO TEST2 1K 1K 1K 47 0.1 0.1 470 0.1 8050 10K 47 IOB3-0 IOB(I/O) IOD7-0 IOD (I/O) VDD(16) VDD(8)
SPDS106A
X'TAL/CERAMIC OSC
C3 20p
IOA3-0 IOA (I/O) IOC6-0 IOC (I/O) TEST1 X32O
XI/R
XO
X32I
20p
X32O
VDD
Battery VDD
20p
SPDS106A
TEST2 IOB3-0 IOB(I/O) (1)VDD1 AUDP AUDN IOD7-0 IOD (I/O) VDD(16) VDD(8) 0.1 VSS(7) VSS(23) R1 VDD 50K C5 RESET 0.1 (3)VSS1 RESET (5)VDD1
SPDS106A
(5)VDD1
AUDP
1K
47
AUDN
1K
47
8050
VSS(7) VSS(23) R2 VDD 50K VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground C3 0.1
(3)VSS1 RESET
8.3. Application Circuit - (3)
(c) Sunplus Technology Co., Ltd.
RESET
SPDS106A single-pin single-ended mode application circuit
Proprietary & Confidential
VDD pad 8, 16 tie together VSS pad 7, 23 tie together VDD1 pad 1, 5 tie together and separately route to power VSS1 pad 3 separately rout to ground
Note: *Capacitor may be increased if necessary. (Cmax = 120p)
0.1
0.1
470
10
(1)VDD1
1K
10K
Version: 1.0
SPDS106A
9. PACKAGE/PAD LOCATIONS
9.1. PAD Assignment
1
VDD1
IOA0 IOA1 IOA2
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
2
AUDP Y
IOA3 IOB0 IOB1 IOB2 IOB3 (0,0) X IOD0 IOD1 IOD2
3 4
VSS1 AUDN
5 6 7 8
VDD1 TEST3 VSS VDD
IOD3 IOD4 IOD5 IOD6 IOD7 TEST1 VSS XO RESET 20 TEST2 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 VDD X32I X32O XI/R 21
9
10
11
12
13
14
15
16
17
18
19
Chip Size: 3160m x 3510m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note3: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
9.2. Ordering Information
Product Number SPDS106A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (A = A - Z).
Package Type Chip form
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SEP. 05, 2001 Version: 1.0
SPDS106A
9.3. PAD Locations
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PAD Name VDD1 AUDP VSS1 AUDN VDD1 TEST3 VSS VDD IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 VDD X32O X32I TEST2 X -1360 -1378 -1378 -1378 -1360 -1378 -1378 -1360 -857 -706 -552 -401 -246 -94 61 214 384 639 849 Y 1573 1123 708 583 133 7 -156 -276 -1515 -1518 -1517 -1517 -1517 -1517 -1517 -1486 -1534 -1534 -1535 PAD No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 PAD Name XI/R XO VSS TEST1 IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 X 1216 1389 1370 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 1386 Y -1535 -1178 -1047 -917 -766 -607 -456 -297 -146 13 164 323 474 632 784 942 1094 1249 1400
RESET
1096
-1536
40
IOA0
1386
1555
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SEP. 05, 2001 Version: 1.0
SPDS106A
10. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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13
SEP. 05, 2001 Version: 1.0
SPDS106A
11. REVISION HISTORY
Date Revision # Description Page
JAN. 29, 2000 SEP. 22, 2000
0.1 0.2
Original 1. 4 interrupt source -> 7 interrupt sources 2. Delete Watchdog timer 3. CPU with 12-bit timers -> CPU with 12-bit timers/counters 4. Operating voltage 2.4V - 5.5V -> 3.6V -> 5.5V 5. Add Volume control function, serial interface I/O, Low voltage reset function
MAY. 15, 2001
0.3
1. Add PIN#5 to VDD1. 2. Add "Note3: The 0.1F capacitor between VDD and VSS ..." 3. Add "REVISION HISTORY" 4. Renew to a new document format
3 9 11
SEP. 05, 2001
1.0
1. Delete "PRELIMINARY" 2. Modify operating voltage: 3.6V - 5.5V -> 2.4V - 5.5V 2. Connect VDD1 to VDD2, and indicate the pin number. 3. Connect VSS1 to VSS2, and indicate the pin number. 4. Origin: Each VDD (total of two) and VSS (total of two) are connected to 0.1F capacitors individually. Modification: Connect two VDD together and similarly, connect two VSS and indicate the pin number. The number of capacitor is reduced to one. 5. Disconnet the VDD and speaker where is reindicated as "Battery VDD". 6. Add note in all application circuits 7. Correct chip size 8. Add Note1 in the "9.1 PAD Assignment" 9. Renew to a new document format 8 - 10 8 - 10 11 11 1, 6 8 - 10 8 - 10 8 - 10
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SEP. 05, 2001 Version: 1.0

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